2009 and Accepted/Submitted

• M.A. Thornton, D.Y. Feinstein. Reversible Logic Synthesis Based on Decision Diagram Variable Ordering, Journal of Multiple-Valued Logic and Soft Computing.
• M.A. Thornton, D.Y. Feinstein and D.M. Miller. Minimization of Quantum Multiple-Valued Decision Diagrams using Data Structure Metrics, Journal of Multiple-Valued Logic and Soft Computing, vol. 15, no. 4, pp. 361-367.
• M.A. Thornton, W. Chen and P. Gui. A Redundant Signed Binary Addition Based Digital-to-Frequency Converter, IEE Electronics Letters, vol. 45, no. 2, pp. 824-826, July 2009.
• M.A. Thornton, A. Fit-Florea, L. Li, and D.W. Matula. A Discrete Logarithm Number System for Integer Arithmetic Modulo 2k: Algorithms and Lookup Structures, IEEE Transactions on Computers, vol. 58, no. 2, Feb. 2009, pp. 163-174.
• M.A. Thornton, W. Chen and P. Gui. A Digital-to-Frequency Converter using Redundant Signed Binary Addition, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2-5, 2009.
• M.A. Thornton, S. Datla and D.W. Matula. A Low Power High Performance Radix-4 Approximate Squaring Circuit, IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), July 7-9, 2009, pp. 91-97.
• M.A. Thornton, D. Feinstein. On the Guidance of Reversible Logic Synthesis by Dynamic Variable Ordering, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 21-23, 2009, pp. 132-138.
• M.A. Thornton, S. Datla, L. Hendrix, and D. Henderson. Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 21-23, 2009, pp. 256-261.
• M.A. Thornton, J. Rice, K. Fazel, K. Kent. Toffoli Gate Cascade Generation Using ESOP Minimization and QMDD-based Swapping, Proceedings of the Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 23-24, 2009, pp. 63-72.
• "A Genetic Algorithm for Autonomous Navigation Using Variable-Monotone Paths", K. H-Sedighi, K. Ashenayi, T.W. Manikas, and R.L. Wainwright, Int. Journal of Robotics and Automation, accepted for publication.
• "An Electrical Engineering Summer Academy for Middle School and High School Students", P. LoPresti, T.W. Manikas, and J. Kohlbeck, IEEE Transactions on Education, accepted for publication.
• "Investigation of Characteristics of Production Pipe as Related to Data Communication in an Oil Well", M. Samiee, K. Ashenayi, and T. Manikas, Proceedings of the 2009 AAAS-SWARM Annual Meeting, 2009.
• "Developing an Autonomous Robot Navigation System Using Genetic Algorithms", B. Gahring, T. Manikas, and K. Ashenayi, Proceedings of the 2009 AAAS-SWARM Annual Meeting, 2009.
• Z. Li, N. Alaeddine and J. Tian, "Multi-Faceted Quality and Defect Measurement for Web Software and Source Contents", Journal of Systems and Software, (to appear), 2009.
• J. Tian, "Feedback Loops for Quality Assurance and Improvement", Software Quality Professional, Vol.11, No. 2, pp.18-26, Mar., 2009.
• J. Tian, S. Nair, L. Huang, N, Alaeddine and M.F. Siok, "Developing Dependable Systems by Maximizaing Component Diversity", In J. Dong, R. Paul and L.-J. Zhang, editors, High Assurance Services Computing, Springer-Verlag, 2009.
• T. Morris, S. Nair, “Encryption Key Protection for Private Computing on Public Platforms”, Proceedings of the Seventh Annual IEEE International Conference on Pervasive Computing and Communications (Percom 2009). Galveston, TX, USA. 9-13 March 2009.
• S. Abu-Nimeh, D. Nappa, X. Wang, S. Nair, "Detecting Phishing Emails via Bayesian Additive Regression Trees", ACM Trans. on Information and System Security (TISSEC), 2008. (Submitted for publication)
• M. Padmaraj, S. Nair, M. Marchetti, G. Chiruvolu, and M. Ali, "Traffic Engineering in Metro Ethernet", Journal of Optical Networks, Special issue on Optical Ethernet, (Submitted for publication)

2008

• M.A. Thornton, D. Easton, V.S.S. Nair, and S.A. Szygenda. A Methodology for Disaster Tolerance Utilizing the Concepts of Axiomatic Design, IIIS Journal of Systemics, Cybernetics and Informatics, vol. 6, no. 4, 2008.
• M.A. Thornton, C.M. Lawler, M.A. Harper, and S.A. Szygenda. Components of Disaster Tolerant Computing: Analysis of Disaster Recovery, IT Application Downtime & Executve Visibility, International Journal of Business Information Systems,vol. 3, no. 3, 2008, pp. 317-331.
• M.A. Thornton, D. M. Miller. Multiple-Valued Logic Concepts and Representations, Morgan & Claypool Publishers, San Rafael, California, ISBN 10-1598291904 (hardcopy), 10-1598291912 (eBook), January 2008.
• M.A. Thornton, J. Moore and D.W. Matula. A Low Power Radix-4 Dual Recoded Integer Squaring Implementation for use in Design of Application Specific Arithmetic Circuits, IEEE Asilomar Conference on Signals, Systems, and Computers (ASILOMAR), October 26-29, 2008, pp. 1819-1822.
• M.A. Thornton, L. Spenner, D. W. Matula, and D. M. Miller. Quantum Logic Implementation of Unary Arithmetic Operations, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 22-23, 2008, pp. 202-207.
• M.A. Thornton, D. Y. Feinstein and D. M. Miller. On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams, IEEE International Symposium on Multiple Valued Logic (ISMVL), May 22-23, 2008, pp. 138-143.
• M.A. Thornton, D. Y. Feinstein and D. M. Miller. Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits, Proceedings of the IEEE/ACM Design, Automation and Test in Europe (DATE), March 10-14, 2008, pp. 1378-1381.
• M.A. Thornton, D.M. Miller. QMDD and Spectral Transformation of Binary and Multiple-Valued Functions, 8th International Workshop on Boolean Problems (IWBP), September 18-19, 2008, pp. 137-144.
• written by David Feinstein, directed by M.A. Thornton. Computer-Aided-Design Methods for Emerging Quantum Computing Techniques, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, April 18, 2008.
• written by Laura Spenner, directed by M.A. Thornton. Quantum Logic Implementation of Unary Arithmetic Operations with Inheritance, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 24, 2008.
• "COOLER- A Fast Multiobjective Fixed-outline Thermal Floorplanner", D. Chatterjee, T.W. Manikas, I. Markov, Proc. 3rd Annual Austin Conf. on Integrated Systems & Circuits (ACISC-08), 2008.
• "Nanobattery-crossbar system, a promising candidate for future nanoscale data storage", P.C. Utekar, T.W. Manikas, and D. Teeters, Proc. 213th ECS (ElectroChemical Society) Meeting, 2008.
• "Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells", T.W. Manikas and D. Teeters, Proc 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL-08), 2008, pp. 197-201.
• "Industry-University Partnerships for Undergraduate Engineering Internships", T.W. Manikas and K. Ashenayi, Proceedings of the 2008 ASEE Midwest Section Conference, 2008.
• "An Electrical Engineering Summer Academy for Middle School and High School Students", P. G. LoPresti, T.W. Manikas, J. Kohlbeck, Proceedings of the 2008 ASEE Midwest Section Conference, 2008.
• N. Alaeddine and J. Tian, "Error Analytic Model for Web Application Reliability Improvement" IASTED Int. Conf. on Internet and Multimedia Systems and Applications, pp.1-6, Kailua-Kuna, HI, Aug., 2008.
• J. Tian, S. Nair, L. Huang, N. Alaeddine, and M. Siok, "Developing Dependable Systems by Maximizing Component Diversity and Fault Tolerance", presentation at the Joint US/UK Workshop on Network-Centric Operation and Network Enabled Capability, Washington, DC, July 24-25, 2008.
• J. Tian, "Software Safety Tutorial", two versions, 1) a progress report presented at the Net-Centric Software Engineering Consortium meeting held at UTD, Richardson, Texas, August 31, 2007; and 2) in I/UCRC format presented at the Net-Centric Software Engineering Consortium meeting held at Raytheon, Plano, Texas, February 1, 2008.
• S. Abu-Nimeh, D. Nappa, X. Wang, S. Nair, "Bayesian Additive Regression Trees-Based Spam Detection for Enhanced Email Privacy", In ARES '08: Proceedings of the 3rd International Conference on Availability, Reliability and Security, pages 1044-1051, 2008
• T. Morris, S. Nair, “Privacy Protected ELF for Private Computing on Public Platforms, IEEE International Conference on Availability, Reliability, and Security, March 2008.
• L. Huang X. Bai S. Nair, “Developing a SSE-CMM-based Security Risk Assessment Process for Patient-Centered Healthcare Systems”, 6th International Workshop on Software Quality, Leipzig, Germany, May, 2008
• M. Padmaraj, S. Nair, M. Marchetti, G. Chiruvolu, and M. Ali, “Bandwidth sensitive fast failure recovery scheme for metro Ethernet”, The International Journal of Computer and Telecommunications Networking, Elsevier Publications, Volume 52 , Issue 8 (June 2008) Pages 1603-1616
• S. Abu-Nimeh, D. Nappa, X. Wang, S. Nair, "A Distributed Architecture for Phishing Detection using Bayesian Additive Regression Trees", eCrime'08, 2008
• J. Tian, S. Nair, L. Huang, N. Alaeddine, and M. Siok, "A Risk-Based Combined Approach to Achieving High Assurance", presentation at the Joint US/UK Workshop on Network-Centric Operation and Network Enabled Capability, Washington, DC, July 24-25, 2008.
• D. Easton, M. Thornton, S. Nair, S. Szygenda, “A Methodology for Disaster Tolerance Utilizing the Concepts of Axiomatic Design”, IIIS Journal of Systemics, Cybernetics and Informatics, 6(4), 2008, Pages 49-53.
• S. Abu-Nimeh, S. Nair, "Bypassing Security Toolbars via DNS Poisoning", IEEE Global Communications Conference (GLOBECOM), Nov. 30- Dec. 4, 2008, Pages 1-6.
• T. Morris, S. Nair, “Private Computing on Public Platforms: Portable Application Security”, IEEE Global Communications Conference (GLOBECOM), Nov. 30- Dec. 4, 2008, Pages ECP.416:1-5.
• S. Abu-Nimeh, S. Nair, "Circumventing Security Toolbars and Phishing Filters via Rogue Wireless Access Points", The Journal of Wireless Communications and Mobile Computing, Wiley InterScience Journals, 2008. (Accepted for publication)
• T. Morris, S. Nair, “Private Computing on Public Platforms”, The Journal of Wireless Communications and Mobile Computing, Wiley InterScience Journals, 2008. (Accepted for publication)

2007

• M.A. Thornton, D.M. Miller and D.Y. Feinstein. QMDD Minimization using Sifting for Variable Reordering, Journal of Multiple-Valued Logic and Soft Computing, vol. 13, no. 4-6, 2007, pp. 537-552.
• M.A. Thornton, L. Li and F. Coyle. UML to SystemVerilog Synthesis for Embedded System Models with Support for Assertion Generation, Proceedings of the ECSI Forum on Design Languages, September 18-20, 2007, Paper 10 on CD-ROM.
• M.A. Thornton, K. Fazel and J.E. Rice. ESOP-based Toffoli Gate Cascade Generation, Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, August 22-24, 2007, pp. 206-209.
• M.A. Thornton, D. Easton, V.S.S. Nair, and J. Stracener. Axiomatic Design in the Biomedical Device Industry, Proceedings of the 11th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI), July 8-11, 2007.
• M.A. Thornton, D. Easton and V.S.S. Nair. Axiomatic Design Process for Disaster Tolerance, Proceedings of the 11th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI), July 8-11, 2007.
• M.A. Thornton, D. Michael Miller and D.Y. Feinstein. Variable Reordering and Sifting for QMDD, IEEE International Symposium on Multiple Valued Logic (ISMVL), May 14-16, 2007, electronic proceedings, Session 2B, paper 1.
• M.A. Thornton, M. Amoui, D. Grosse, and R. Drechsler. Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL, IEEE International Symposium on Multiple Valued Logic (ISMVL), May 14-16, 2007, electronic proceedings, Session 8B, paper 2.
• M.A. Thornton, C.M. Lawler and S.A. Szygenda. Techniques for Disaster Tolerant Information Technology Systems, IEEE Systems Conference, April 9-12, 2007, pp. 333-338.
• M.A. Thornton, M.A. Harper and S.A. Szygenda. Disaster Tolerant Systems Engineering for Critical Infrastructure Protection, IEEE Systems Conference, April 9-12, 2007, pp. 2-8.
• M.A. Thornton, D. Feinstein and F. Kocan. System-on-Chip Power Consumption Refinement and Analysis, Proceedings of the IEEE Dallas Workshop on Circuits and Systems, November 15-16, 2007, pp. 81-84.
• M.A. Thornton, D. Goodman, D.Y. Feinstein, and D.M. Miller. Quantum Logic Circuit Simulation Based on the QMDD Data Structure, Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 16, 2007, pp. 99-105.
• M.A. Thornton, D.Y. Feinstein. ESOP Transformation to Majority Gates for Quantum-dot Cellular Automata Logic Synthesis, Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 16, 2007, pp. 43-50.
• M.A. Thornton, C.M. Lawler and M.A. Harper. Components of Disaster Tolerant Computing, International Workshop on Information Assurance, in conjunction with the IEEE International Performance Computing and Communications Conference, April 11-13, 2007, pp. 380-386.
• M.A. Thornton, D. Y. Feinstein and V.S.S. Nair. Advances in Quantum Computing Fault Tolerance and Testing, IEEE High Assurance Systems Engineering Symposium (HASE), November 14-16, 2007, pp. 369-370.
• written by P. Kulkarni, directed by M.A. Thornton. Hardware Acceleration of Software Library String Functions, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, December 2007.
• written by K. Hawkins, directed by M.A. Thornton. An Automated Tool for HDL and Configuration File Generation from UML System Descriptions, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, June 2007.
• written by D. Goodman, directed by M.A. Thornton. A Quantum Logic Simulator Based on Decision Diagrams, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 2007.
• M.A. Thornton, D.W. Matula, A. Fit-Florea, and L. Li. Determining a Table Output of a Table Representing a Hierarchical Tree for an Integer Valued Function, Patent Pending, Patent Application No. 20080005211, Filed June 26, 2007.
• "Genetic Algorithms for Autonomous Robot Navigation", T.W. Manikas, K. Ashenayi, and R.L. Wainwright, IEEE Instrumentation & Measurement Magazine, vol. 10, no. 6, Dec. 2007, pp. 26-31 (invited paper).
• "A Genetic Algorithm for Non-Slicing Floorplan Representation", D. Chatterjee and T.W. Manikas, Proc. Nat. Conf. on Intelligent Systems (NCIS), 2007.
• "Nanoscale Power and Memory Unit Design for Nanoscale Sensor Systems", T.W. Manikas and D. Teeters, Proc. 53rd ISA Int. Instrumentation Symp., 2007.
• "Power-Density Aware Floorplanning for Reducing Maximum On-Chip Temperature", D. Chatterjee and T.W. Manikas, Proc. 18th IASTED Int. Conf. on Modelling and Simulation, 2007.
• "Developing and Funding Undergraduate Engineering Internships", T.W. Manikas and G.R. Kane, Proceedings of the 2007 ASEE Midwest Section Conference, 2007.
• L. Ma and J. Tian, "Web Error Classification and Analysis for Reliability Improvement", Journal of Systems and Software, Vol.80, No.6, pp.795-804, June, 2007.
• J. Tian, "From Quality Assurance to Software Quality Engineering", Software Quality Professional, Vol.9, No. 2, pp.17-26, Mar., 2007.
• N. Alaeddine and J. Tian, "Analysis of Anomalies and Failures in Dynamic Web Applications", IASTED Int. Conf. on Software Engineering and Applications, pp.385-390, Cambridge, MA, Nov., 2007.
• M.F. Siok and J. Tian, "Empirical Study of Embedded Software Quality and Productivity", 10th IEEE Int. Symposium on High Assurance Systems Engineering (HASE'07), Dallas, TX, pp.313-320, Nov., 2007.
• N. Alaeddine and J. Tian, "Analytic Model for Web Anomalies Classification" 10th IEEE Int. Symposium on High Assurance Systems Engineering (HASE'07), pp.395-396, Dallas, TX, Nov., 2007.
• J. Tian, "A Risk-Based Combined Approach to Achieving High Assurance", panel presentation at the 10th IEEE Int. Symposium on High Assurance Systems Engineering (HASE'07), panel on "Achieving High Assurance: Formal, Informal, and Combined Approaches", Dallas, Texas, Nov. 15, 2007.
• J. Tian, "Risk-Based Quantifiable Quality Improvement", presentation (summary of Jeff Tian's research) at the Net-Centric Software Engineering Consortium meeting held at Raytheon, Plano, Texas, March 30, 2007.
• T. Morris, V. S. S. Nair, PCPP: Private Computing on Public Platforms, A New Paradigm in Public Computing, IEEE International Symposium on Wireless Pervasive Computing 2007, February 2007.
• J. Kennington, V. S. S. Nair, and G. Spiride. Optimal spare capacity assignment for path restorable mesh networks: Cuts, decomposition, and an empirical analysis. International Journal on Parallel and Distributed Systems and Networks, Vol. 29, pages 170-179, 2007.
• T. Morris, V. S. S. Nair, “PCPP: On Remote Host Assessment via Naive Bayesian Classification”, IEEE, ACM International Parallel & Distributed Processing Symposium (IPDPS), International Workshop on Security in Systems and Networks, March 2007 Page(s):1 – 8
• D. Easton, M. Thornton V.S.S. Nair, and J. Stracener, Axiomatic Design in the Biomedical Device Industry, Proceedings of the 11th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI), July 8-11, 2007.
• D. Easton M. Thornton and V.S.S. Nair, Axiomatic Design Process for Disaster Tolerance, Proceedings of the 11th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI), July 8-11, 2007.
• S. Abu-Nimeh, D. Nappa, X. Wang and S. Nair, Phishing Detection: An Experimental Study, ACM International Conference Proceeding Series; Vol. 269, Proc. of The 2nd APWG eCrime Researchers Summit, Pittsburg, PA, Oct. 2007, Pages 60-69.
• D. Feinstein, S. Nair, M. Thornton, Advances in Quantum Computing Fault Tolerance and Testing, Proc. 10th IEEE High Assurance Systems Engineering Symposium (HASE 2007), Nov. 2007, Plano, Texas.

2006

• M.A. Thornton, L. Li and S. Szygenda. Integrated Design Validation: Combining Simulation and Formal Verification in Integrated Circuit Design, IIIS Journal of Systemics, Cybernetics and Informatics, vol. 4, no. 2, 2006.
• M.A. Thornton, R. B. Reese. Introduction to Logic Synthesis Using Verilog HDL, Morgan & Claypool Publishers, San Rafael, California, ISBN 10-1598291068 (hardcopy), ISBN 10-1598291076 (eBook), November 2006.
• M.A. Thornton, R.B. Reese. Method for Early Evaluation in Micropipeline Processors, Patent No. 7,043,710 B2, May 9, 2006.
• M.A. Thornton, L. Li, A. Fit-Florea, and D.W. Matula. Performance Evaluation of a Novel Table Lookup Method and Architecture for Integer Functions, IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 99-104, September 11-13, 2006.
• M.A. Thornton, D.M. Miller and D. Goodman. A Decision Diagram Package for Reversible and Quantum Circuit Simulation, IEEE Congress on Evolutionary Computation, IEEE World Congress on Computational Intelligence (WCCI), July 16-21, 2006, pp. 8597-8604 on Proceedings CD-ROM (best paper of session).
• M.A. Thornton, D.M. Miller. QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 17-20, 2006, pp. 30-30 on Proceedings CD-ROM.
• M.A. Thornton, L. Li and M. Perkowski. A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 17-20, 2006, pp. 33-33 on Proceedings CD-ROM.
• M.A. Thornton, L. Li and D.W. Matula. A Digit Serial Algorithm for the Integer Power Operation, ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), April 30-May 2, 2006, pp. 302-307.
• written by Lun Li, directed by M. A. Thornton. Integrated Techniques for the Formal Verification and Validation of Digital Systems, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, May 2006.
• “Evolving A Diverse Collection of Robot Path Planning Problems”, D. Ashlock, T.W. Manikas, and K. Ashenayi, Proc. 2006 IEEE Congress on Evolutionary Computation, 2006.
• “A Genetic Algorithm for Binary Decision Diagram Variable Ordering”, C.M. Linnet and T.W. Manikas, Proceedings of the 81st AAAS-SWARM Annual Meeting, 2006.
• M.F. Siok, C.J. Whittaker and J. Tian, "Exposing Software Field Failures", CrossTalk: The Journal of Defense Software Engineering, Vol.19, No.11, pp.15-20, Nov., 2006.
• J. Tian and L. Ma, "Web Testing for Reliability Improvement", in Advances in Computers, Vol.67, pp.177-224, Academic Press, 2006.
• How Much Software Quality Investment Is Enough: A Value-Based Approach
  LiGuo Huang and Barry Boehm
  IEEE Software, vol. 23, no. 5, September/October, 2006, pp. 88-95.
• Applying the Value/Petri Process to ERP Software Development in China
  LiGuo Huang, Barry Boehm, Hao Hu, Jidong Ge, Jian Lü, Cheng Qian
  Proceedings of 28th International Conference of Software Engineering (ICSE), Shanghai, China, May 2006.
• Tailor the Value-Based Software Quality Achievement Process to Project Business Cases
  LiGuo Huang, Hao Hu, Jidong Ge, Barry Boehm, Jian Lü
  Proceedings of International Software Process Workshop (SPW), co-located with ICSE, Shanghai, China, May 2006, LNCS.
• G. Deprez, M. Padmaraj, S. Nair, "Restoration Protocol for Heterogeneous Networks", IEEE AICCSA, March 2006
• M. Ali, , G. Chiruvolu, A. Ge, M. Padmaraj, S. Nair, and M. Marchetti "Differentiated Survivability in Ethernet-Based MAN/WAN", IEEE AICCSA, March 2006
• S. Abu-Nimeh, S. Nair, and M. Marchetti, "Avoiding Denial of Service via Stress-testing", IEEE, AICCSA-06, March, 2006
• S. Abu-Nimeh, S. Nair, and M. Marchetti, "An Experimental and Industrial Experience: Avoiding Denial of Service via Memory profiling", IEEE, AICCSA-06, March 2006
• M. Padmaraj, S. Nair, M. Marchetti, G. Chiruvolu, and M. Ali, "Distributed Fast Failure Recovery Scheme for Metro Ethernet", IEEE ICN, April 2006
• S. Abu-Nimeh, S. Nair, “Phishing the Airwaves: Phishing Wireless Devices”, The APWG (Anti-Phishing Working Group) 2006 Spring General Meeting and Email Authentication Summit in Chicago, IL.
• S. Abu-Nimeh, S. Nair, "Phishing Attacks in a Mobile Environment", Mobile Antivirus Researchers Association (MARA), White Paper, 2006.
• S. Nair, Ebru Celikel, Marco Marchetti, Adaptive Security and Reliability using Linear Erasure Correction Codes, Proceedings of 7th International Business Information Management Conference (7th IBIMA), Brescia, Italy, Dec,. 2006

2005

• M.A. Thornton, R. B. Reese and C. Traver. A Coarse-Grain Phased Logic CPU, IEEE Transactions on Computers, vol. 54, no. 7, July 2005, pp. 788-799.
• M.A. Thornton, R. B. Reese, C. Traver, and D. Hemmendinger. Early Evaluation for Performance Enhancement in Phased Logic, IEEE Transactions on Computer Aided Design, (vol. 24, no. 4, pp. 532-550, April 2005.
• M.A. Thornton, A. Fit-Florea and D.W. Matula. Additive Bit-serial Algorithm for the Discrete Logarithm Modulo 2k, IEE Electronics Letters, vol. 41, no. 2, pp. 57-59, January 2005.
• M.A. Thornton, A. Fit-Florea and D.W. Matula. Addition-based Exponentiation Modulo 2k, IEE Electronics Letters, vol. 41, no. 2, pp. 56-57, January 2005.
• M.A. Thornton, L. Li and S. Szygenda. BDD-Based Conjunctive Decomposition Using a Genetic Algorithm and Dependent Variable Affinity, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 24-26, 2005, pp. 277-280.
• M.A. Thornton, K. Fazel and R.B. Reese. Early Evaluation for Phased Logic Circuits Using BDDs and MVL, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 24-26, 2005, pp. 400-403.
• M.A. Thornton, M. Gunes, F. Kocan, and S.A. Szygenda. A Survey and Comparison of Digital Logic Simulators, IEEE Mid-West Symposium on Circuits and Systems (MWSCAS), August 7-10, 2005, p. 156 (abstract), full paper on Proceedings CD-ROM.
• M.A. Thornton, S. Szygenda. Disaster Tolerant Computing and Communications, International Conference on Cybernetics and Information Technologies, Systems and Applications (CITSA 2005), and International Conference on Information Systems Analysis and Synthesis (ISAS), July 14-17, 2005, pp. 171-173.
• M.A. Thornton, M. A. Harper and C. Lawler. IT Application Downtime, Executive Visibility and Disaster Tolerant Computing, International Conference on Cybernetics and Information Technologies, Systems and Applications (CITSA 2005), and International Conference on Information Systems Analysis and Synthesis (ISAS), July 14-17, 2005, pp. 165-170.
• M.A. Thornton, L. Li and S. Szygenda. Combining Simulation and Formal Verification for Integrated Circuit Design Validation, 9th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI), July 10-13, 2005, pp. 92-97.
• M.A. Thornton, D.W. Matula and A. Fit-Florea. Lookup Table Structures for Multiplicative Inverses Modulo 2k, IEEE Symposium on Computer Arithmetic (ARITH), June 27-29, 2005, pp. 130-135.
• M.A. Thornton. The Karhunen-Loève Transform of Discrete MVL Functions, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 18-21, 2005, pp. 194-199.
• M.A. Thornton, L. Li, A. Fit-Florea, and D.W. Matula. Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2k, IEEE Symposium on VLSI (ISVLSI), May 10-11, 2005, pp. 130-135.
• M.A. Thornton, F.P. Coyle. A Framework and Process for Curricular Integration and Innovation Using Project Based Interdisciplinary Teams, International Conference on Information Technology (ITCC), April 4-6, 2005, pp. 432-435.
• M.A. Thornton, F.P. Coyle. From UML to HDL: a Model Driven Architectural Approach to Hardware-Software Co-Design, Information Systems: New Generations Conference (ISNG), April 4-6, 2005, pp. 88-93.
• “Benchmarking of Robot Path Planning Algorithms”, A. Hand, J. Godugu, K. Ashenayi, T.W. Manikas, and R.L. Wainwright, in Intelligent Engineering Systems Through Artificial Neural Networks: Smart Engineering Systems Design: Neural Networks, Fuzzy Logic, Evolutionary Programming, Complex Systems and Artificial Life, C.H. Dagli, et al., Editors. Vol. 15, 2005, ASME Press: New York.
• “Developing Laboratory Courses in a Resource-Constrained Environment”, T.W. Manikas, D.E. Jussaume, and G.R. Kane, Proceedings of the 2005 ASEE Midwest Section Conference, 2005.
• Jeff Tian, "Software Quality Engineering: Testing, Quality Assurance, and Quantifiable Improvement", John Wiley and Sons, Inc. and IEEE Computer Society Press, 2005. ISBN: 0-471-71345-7.
• A.G. Koru and J. Tian, "Comparing High-Change Modules and Modules with the Highest Measurement Values in Two Large Scale Open-Source Products", IEEE Trans. on Software Engineering, Vol.31, No.8, pp.625-642, Aug., 2005.
• J. Tian, "Risk-Based Quality Improvement for Embedded Systems", panel presentation at the International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, Sept.29-Oct.1, 2005.
• J. Tian. "Software Quality Management", tutorial at Tec de Monterrey faculty development workshop. Monterrey, Mexico, May 31 - June 3, 2005.
• A Value-Based Process for Achieving Software Dependability
  LiGuo Huang
  Proceedings of International Software Process Workshop (SPW), co-located with ICSE, Shanghai, China, May 2005, LNCS3840.
• M. Padmaraj, S. Nair, M. Marchetti, G. Chiruvolu, M. Ali. "Traffic Engineering in Enterprise Ethernet with Multiple Spanning Tree Regions," icw, pp. 261-266, 2005 Systems Communications (ICW'05, ICHSN'05, ICMCS'05, SENET'05), 2005.
• M. Padmaraj; S. Nair; M. Marchetti; G. Chiruvolu; M. Ali; A. Ge; "Metro Ethernet traffic engineering based on optimal multiple spanning trees", Wireless and Optical Communications Networks, 2005. WOCN 2005. Second IFIP International Conference on 6-8 March 2005 Page(s):568 - 572
• G. Deprez, M. Padmaraj, S. Nair, "Net Planner: A Capacity Allocation Tool", Telecommunications, 2005. ConTEL 2005. Proceedings of the 8th International Conference on Volume 1, June 15-17, 2005 Page(s):147 - 154
• M. Padmaraj, S. Nair, M. Marchetti, G. Chiruvolu, and M. Ali, "Simulation of recovery scheme for Metro Ethernet", In Proceedings of OPNETWORKS'05, August 2005
• M. Ali, , G. Chiruvolu, M. Padmaraj, S. Nair, and M. Marchetti "Augmented Hose Model for Metro Ethernet", In proceedings of IEEE ICON, November 2005

Selected Pre-2005

• M.A. Thornton. Microprocessor Systems, Article in the Encyclopedia of Life Support Systems, EOLSS Publishers Co. Ltd., March 2003.
• M.A. Thornton, R. Drechsler and D. M. Miller. Spectral Techniques in VLSI CAD, Kluwer Academic Publishers, Boston, Massachusetts, ISBN 0-7923-7433-9, July 2001.
• M.A. Thornton, D. L. Andrews. Multiprocessor Memory Resource Estimation, Chapter 10 in Parallel and Distributed Systems: Architectures, Tools and Algorithms, Jose Aguilar, Editor, IIIS Publishers, ISBN 980-07-5956-5, July 2001.
• M.A. Thornton, D. L. Andrews, J. M. Conrad and M. D. Glover. Computer-Aided Engineering and Design, Chapter 8 in ADVANCED ELECTRONIC PACKAGING: With Emphasis on Multi-Chip Modules, W. D. Brown, Editor, IEEE Press, Piscataway, New Jersey, ISBN 0-7803-4700-5, 1999.
• M.A. Thornton, F. Kocan and M. Gunes. Static Variable Ordering in ZBDDs for Path Delay Fault Coverage Calculation, IEEE Mid-west Symposium on Circuits and Systems (MWSCAS), July 25-28, 2004, pp. I-509 - I-512.
• M.A. Thornton, R. Marczynski and S. Szygenda. Test Vector Generation and Classification Using FSM Traversals, IEEE International Symposium on Circuits and Systems (ISCAS), May 23-26, 2004, pp. V-309 - V-312.
• written by Satyendra Datla, directed by M. A. Thornton. Crosstalk Delay Analysis in Very Deep Submicron VLSI Circuits, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 2004.
• written by Kenneth B. Fazel, directed by M. A. Thornton. Performance Enhancement Techniques for Phased Logic Circuits, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 2004.